1. Field of the Invention
This invention relates to integrated circuit structures. More particularly this invention relates to an integrated circuit structure having reduced soft error rate.
2. Description of the Related Art
As integrated circuit structures reduce down to sub 0.25 xcexcm linewidths and the supply voltage (operating voltage) is reduced to less than xcx9c2 volts, memory/logic devices are more prone to alpha particle-induced soft errors. The smaller the device size and the lower the supply voltage, the smaller the critical charge (Qcrit) will be for the device, where the critical charge (Qcrit) is the largest charge which can be injected into a memory array storage cell without changing the cell""s logic state. Reduction of the soft error rate (SER) is, therefore, becoming more important as the memory device size shrinks and operating voltages are reduced.
The problem of alpha particle collisions is of particular concern with regard to N-channel transistors formed in P wells because of the higher mobility of electrons in silicon compared to holes, i.e, the electron in the electron-hole pair generated by the alpha particle collision is more likely to reach the N+ diffusion regions of the N channel transistor than is the corresponding hole to reach the P+ diffusion regions of a P channel transistor. Furthermore, in view of this greater sensitivity of N channel transistors to the problem of alpha particle collisions, the problem is further exacerbated for memory cells because of the preference for using N channel transistors in memory cells due to their faster speed. FIG. 1 shows a cross-section of a typical SRAM containing both N channel and P channel transistors. A first N well 8, a P well 10, and a second N well 12 are shown formed in a silicon semiconductor substrate 2. A first P channel transistor 20 formed in the surface of first N well 8 comprises P+ source/drain regions 22 and 24 separated by a gate electrode 26 formed over a channel region in first N well 8. Separated from P channel transistor 20 by field oxide portions 6 is an N channel transistor 30 formed in the surface of P well 10 comprising N+ source/drain regions 32 and 34 separated by a gate electrode 36 formed over a channel region in P well 10. A second P channel transistor 40 formed in the surface of second N well 12 and separated from N channel transistor 30 by field oxide 6 comprises P+ source/drain regions 42 and 44 separated by a gate electrode 46 formed over a channel region in second N well 12.
The path or trajectory of an alpha-particle is shown passing through transistor 40 and substrate 2 at A in FIG. 1, with electron-hole pairs shown generated by collisions between the alpha-particle and the silicon atoms of the substrate. If sufficient electrons generated by these collisions migrate to the N+ source/drain diffusion regions 32 and 34 of N channel transistor 30, the accumulated charge on the N+ regions 32 and 34 can cause an erroneous reading of the charge state (off/on state) of the SRAM cell, i.e., cause a soft error to occur.
In DRAM structures in the past, reduction in the soft error rate has been achieved in several ways. Y. Matsuda et al. et al., in xe2x80x9cMeV-Boron Implanted Buried Barrier for Soft Error Reduction in Megabit DRAMxe2x80x9d, published in Extended Abstracts of the 19th Conference on Solid State Devices and Materials, Tokyo, (1987) at pages 23-26, describe the use of a buried layer of implanted boron in a Pxe2x88x92 substrate to reduce the soft error rate in a DRAM cell.
More recently, T. Yamashita et al., in xe2x80x9cSubstrate Engineering for Reduction of Alpha-Particle-Induced Charge Collection Efficiencyxe2x80x9d, published in the Japan Journal of Applied Physics, at Volume 35, Part 1, No. 2B (1996) at pages 869-873, identified three schemes for reducing charge collection efficiency (by the N+ diffusion regions of the DRAM memory cell). They state that charge collection efficiency (CCE) may be reduced by preventing minority carriers from traveling toward the diffusion layer; or by absorbing minority carriers by an extra fabricated layer; or by killing minority carriers before they reach the diffusion layer.
They then describe several structures which have been used for carrying out the above schemes to attain soft error reduction in DRAM memory cells, including a retrograde P well structure, a double well construction with an N well formed below the P well in a Pxe2x88x92 substrate, a P well in a Pxe2x88x92 epitaxial layer grown on a P+ substrate, and a buried defect layer formed below a P well. The buried defect layer is formed by high dosage implant of high energy silicon or boron ions into the substrate.
With respect to the double well construction, Yamashita et al. state that the CCE for the double well construction is much lower than that of the simple retrograde well. They then note that the alpha-particle-induced electrons coming from deep inside the substrate are not collected in the diffusion layer but accumulate in the bottom n-layer of the double well construction, indicating that the bottom n-layer is found to act as an effective shield for minority carriers, even in the case of high-level injection such as the incidence of alpha-particles. They then further observe that the CCE for the double well construction of 2 xcexcm depth is lower than that of the double well of 3 xcexcm depth, and state that it is, therefore, considered to be more effective to put this absorptive bottom n-layer near the surface for reduction in soft error rate.
With respect to the buried defect layer, Yamashita et al. after stating that the CCE for the P well with a buried layer is much lower than that for a simple P well, observe that the lattice defects induced by the implantation are considered to play an important role since silicon implantation, which does not give rise to a potential difference in the substrate, as well as boron implantation, both reduce CCE. They then indicate that these defects are considered to act as minority carrier killers.
Yamashita et al. then conclude that CCE for the double well is low because the bottom n-layer acts as an effective absorber for minority carriers, and that the CCE for a P well with a heavily doped buried layer fabricated by high-energy and high-dosage ion implantation is as low as that for a double well because the carrier lifetime is short in the buried layer due to lattice defects, and that it is more effective to fabricate the bottom n-layer or the buried layer near the surface to reduce CCE.
While the foregoing structures solved or at least mitigated the problem of alpha-particle-induced soft errors in DRAMS, similar soft error rate (SER) problems induced by alpha-particle radiation were not noted in at least some of the SRAM structures until recently in connection with the scaling down to the sub-0.25 xcexcm regime. In view of such prior art teachings concerning the use of a buried defect layer to solve SER problems in DRAMs, this buried layer approach was experimented with in SRAM structures. Quite surprisingly, the addition of a buried defect layer beneath the P well of an SRAM structure was found to have little if any benefit in reducing SER.
Upon further consideration and comparison of the conventional prior art DRAM construction, it was concluded that the reason why the addition of a buried layer to the prior art SRAM structure did not reduce the soft error rate (unlike the prior art DRAM) may be due to the presence of both N wells and P wells in a prior art SRAM structure as shown in FIG. 1, compared to the single well of a prior art DRAM, which is usually a P well so that a faster N channel transistor may be constructed therein.
It was concluded that the presence of N wells in the prior art SRAM might be already providing the same amount of SER reduction in an SRAM as does the buried layer in a DRAM, thus rendering the addition of a buried layer in an SRAM construction superfluous. It was further concluded that the soft errors now being noted in the SRAM construction were not previously noted in larger scale devices because the larger problem of deep electron penetration was being addressed by either the buried layer of the DRAM cell or the N well regions of the SRAM construction, and because the lower Qcrit charge in smaller scale devices now made the present problem more noticeable.
The problem of reduction of the SER in integrated circuit structures such as, for example, sub 0.25 xcexcm SRAM structures beyond the previously achieved reductions thus remained to be solved in a different manner.
The invention comprises an improved integrated circuit structure, such as a SRAM construction, wherein the soft error rate is reduced. The improved SRAM of the invention is formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to at least one deep N well connected to the high voltage and the deep N well extends from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a typical 0.25 xcexcm SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 xcexcm, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 xcexcm. In accordance with the invention, the deep N well of the invention, therefore, extends down from the substrate surface a distance of at least about 0.5 xcexcm, and preferably at least about 2 xcexcm. In a preferred embodiment, the implantation of the substrate to form the deep N well of the invention is carried out in a manner which will cause lateral straggle, i.e., cause the doped volume comprising the deep N well to broaden at its base. Such a broadened base deep N well will have enhanced opportunity to collect electrons generated by the alpha particle collisions with the substrate. This deep N well with a broadened base can be formed either by increasing the implant energy or by tilting the substrate with respect to the axis of the implant beam while implanting the substrate to form the deep N well.